Datasheet

Power Up and Reset Sequence
Intel
®
Quark™ microcontroller D2000
Datasheet January 2016
82 Document Number: 333577-002EN
11. FW to configure RAR Voltage regulator to operate in retention mode (Linear
Regulator). This step is needed as RAR in eSR switching regulator mode is
very inefficient (consumes more power) at low current loads.
a. Set ROK_BUF_VREG_MASK as AON_VR.ROK_BUF_VREG would go low
during retention mode. This ensures that logic that uses
ROK_BUF_VREG output from RAR are not falsely triggered.
b. Set AON_VR.VREG_SEL to qLR/retention mode. VSEL_IN is set to
1.8V. VSEL_STROBE strobing is not required here as voltage is not
changed. Don’t do any voltage programming of RAR as Retention
voltage less than 1.8V is not POR, as it would make all IO pads non-
functional. After 20 usec (no need to wait for this time), RAR would
come up in qLR retention mode delivering 300 uA max current.
External tank capacitor ensures that DVDD supply is maintained
without any drops or droops during this transition.
12. If wake source is any of AON Timer, RTC, GPIO interrupt, program
CCU_SYS_CLK_CTL.CCU_SYS_CLK_SEL to RTC Oscillator. This step is not
needed if wake source is only comparator and/or GPIO level triggered
interrupt (without GPIO debouncing).
13. SW/FW to execute HALT instruction.
a. Once core is halted, PMU will automatically clock gate processor clock
and memory subsystem clock. This reduces dynamic power consumed
by processor and memory subsystems (provided CCU_LP_CLK_CTL.
CPU_CPU_HALT_EN and CCU_LP_CLK_CTL.CPU_MEM_HALT_EN are
enabled). And also PMU will power down Hybrid oscillator and RTC
Oscillator as per respective OSC0_PD and OSC1_PD register bits.