Datasheet

Power Up and Reset Sequence
Intel
®
Quark™ microcontroller D2000
January 2016 Datasheet
Document Number: 333577-002EN 81
3. SW/FW must enable the needed interrupt sources for wake and mask all other
interrupt sources. Wake sources can be any of enabled low power
comparators, any GPIO based interrupt wake, AON Periodic Timer expiry, RTC
alarm interrupt. Additionally system automatically wakes up to RST_N
assertion.
a. Program WAKE_MASK.WAKE_MASK[31:0],
CCU_LP_CLK_CTL.WAKE_PROBE_MODE_MASK registers identical to
Interrupt Mask registers.
4. Program HYB_OSC_PD_LATCH_EN = 0, RTC_OSC_PD_LATCH_EN=0. This
ensures that powering down of oscillators is delayed by hardware till core
executes HALT at last step in this sequence.
5. Program CCU_LP_CLK_CTL.CCU_EXIT_TO_HYBOSC to 1’b1. This ensures that
at exit, hardware will switch system clock to Hybrid oscillator clock so as to
minimize exit latency by running at higher frequency than RTC clock.
6. If RTC clock is not needed during low power state (no AON Timer, RTC, GPIO
interrupt), FW to program OSC1_CFG0.OSC1_PD to 1’b1. RTC Oscillator will
actually get powered down only at last step when core enters HALT.
7. FW to program OSC0_CFG1.OSC0_PD = 1. Hybrid Oscillator will actually get
powered down only at last step when core enters HALT.
8. FW configures Hybrid Oscillator (OSC0_CFG0/1 registers) to 4 MHz Silicon
oscillator mode while applying trimcode specific to 4MHz frequency. Note that
Hybrid oscillator shall not be disabled to effect this change if
CCU_SYS_CLK_SEL is set to hybrid oscillator as it stops the clock to processor.
This step ensures that current consumed by hybrid oscillator is reduced to
~180 uA levels as max retention mode current supply from RAR is 300 uA.
9. FW sets CCU_SYS_CLK_CTL.CCU_SYS_CLK_DIV to div-by-32 (or lower; TBC)
to reduce system clock frequency to 125 kHz (or lower; TBC). This step is
needed to reduce dynamic power of processor and digital logic so that overall
current draw by SoC is now less than 300 uA.
10. If (retention voltage in low power state == 1.35V) { // change to 1.35V in
eSR mode. This step is not needed if retention voltage is unchanged at 1.8V
itself.
a. FW to move HYBOSC to low voltage retention mode.
SCSS.OSC0_CFG0.OSC0_HYB_SET_REG1.OSC0_CFG0[0] = 1;
b. FW to Put Flash to LVE mode from Normal Voltage mode
FlashCtrl.CTRL.LVE_MODE = 1;
c. FW to set SCSS.AON_VR.VSEL = 0xB; // Set to 1.35V. This will take
effect only with VSEL_STROBE. Perform read modify write along with
passcode.
d. FW to set SCSS.AON_VR.ROK_BUF_VREG_MASK = 1; // Perform read
modify write along with passcode.
e. FW to do Voltage strobing in next access to AON_VR register after
setting up VSEL previously.
SCSS.AON_VR.VSEL_STROBE = 1; // Bit 5. Perform read mod write
along with passcode
f. Wait for 1 usec;
g. FW to reset SCSS.AON_VR.VSEL_STROBE = 0; // Bit 5. Perform read
mod write along with passcode
h. Wait for 2 usec; // Wait for 1.35V to take effect