Datasheet

Power Up and Reset Sequence
Intel
®
Quark™ microcontroller D2000
Datasheet January 2016
80 Document Number: 333577-002EN
9.2.1 Active to Any Low Power State
For those low power states not requiring voltage regulator to be put into retention
mode, the following sequences are not required and can be handled by SW/FW by
powering down or enabling clock gating of specific components not in use based on
System Power State. For example, Low Power Halt state is mainly halting processor
and optionally memory system by executing HALT instruction while peripherals can be
in operation.
Whenever user application / software wants to enter any of low power state (having
voltage regulator in retention mode) from ACTIVE state, the following sequence
occurs: All steps are executed by Firmware.
1. SW/FW to ensure all interrupts are serviced and no interrupt pending.
2. SW/FW to ensure that all high power components such as ADC, high-
performance comparators ([5:0]), unneeded low power comparators (18:6]),
are powered down and peripheral subsystem clock gated (PERIPH_CLK_EN =
0).