Datasheet

Power Up and Reset Sequence
Intel
®
Quark™ microcontroller D2000
January 2016 Datasheet
Document Number: 333577-002EN 79
One or more possible wake sources can be simultaneously enabled in a given low
power state. RST_N assertion will automatically transition the SoC to normal/active
state (4 MHz Si OSC mode) as given in section 9.1.1.
Low Power State Possible Wake Sources
Deep Sleep RTC state AON Periodic Timer (AONPT), RTC Alarm, GPIO
Edge/Level triggered interrupt (with or without GPIO
debouncing), Comparator, CLTAP Probe mode request
through JTAG , RST_N assertion.
Deep Sleep NoRTC
state
GPIO Level triggered interrupt (without GPIO
debouncing), Comparator interrupt, CLTAP Probe mode
request through JTAG, RST_N assertion.
CLTAP Probe mode request is generated by setting CLTAP_CPU_VPREQ.assert_vpreq
to 1 (TAP instruction 0x70 Bit0) through JTAG interface. In deep sleep state, ensure
TCK frequency is less than 32 kHz (system clock frequency at that state divided by 4).
For setting GPIO level triggered interrupt as wake source, GPIO controller has to be
programmed as below for a specific GPIO pin x of interest:
• GPIO_INTEN[x] = 1. Enable interrupt for that particular GPIO pin.
• GPIO_INTYPE_LEVEL[x] = 0; Level sensitive interrupt.
• GPIO_INT_POLARITY[x] = 1; Active-high level interrupt (0 to 1 on GPIO pin
will wake; default state of this GPIO input pin shall be 0). Set this register bit
to 0 if it has to be active-low level interrupt. 0 level to trigger interrupt.
• GPIO_DEBOUNCE[x] = 0. No debounce as there is no clock running.
GPIO_LS_SYNC[x] = 0. Not synchronized as there is no clock running to synchronize.
(d) and (e) are important settings.