Datasheet

Power Up and Reset Sequence
Intel
®
Quark™ microcontroller D2000
Datasheet January 2016
78 Document Number: 333577-002EN
9. FW has to bring back RAR voltage regulator to eSR normal mode before it
enables other SoC components for normal mode of operation.
a. Set AON_VR.VREG_SEL to eSR/normal mode.
b. Wait for 2 usec (TBC) for RAR to switch back to eSR normal mode
delivering up to 50 mA max current.
c. Clear AON_VR.ROK_BUF_VREG_MASK.
10. If (SCSS AON_VR.VSEL == 1.35V) { // exiting from 1.35V core voltage mode
a. FW to set SCSS.AON_VR.VSEL = 0x10; // Set to 1.8V. This will take
effect only for VSEL_STROBE. Perform read modify write along with
passcode.
b. FW to do Voltage strobing in next access to AON_VR register after
setting up VSEL previously.
SCSS.AON_VR.VSEL_STROBE = 1; // Bit 5. Perform read mod write
along with passcode
c. Wait for 1 usec;
d. FW to reset SCSS.AON_VR.VSEL_STROBE = 0; // Bit 5. Perform read
mod write along with passcode
e. Wait for 2 usec; // Wait for 1.8V to take effect
f. FW to reset SCSS.AON_VR.ROK_BUF_VREG_MASK = 0; // Perform
read modify write along with passcode.
g. Wait for 1 usec; // 1 usec for DVDD to be stable at 1.8V before
changing HYBOSC and Flash low voltage mode.
h. FW to move HYBOSC from low voltage retention mode to normal 1.8V
mode. SCSS.OSC0_CFG0.OSC0_HYB_SET_REG1.OSC0_CFG0[0] = 0;
i. FW to Put Flash from LVE mode to Normal Voltage mode
FlashCtrl.CTRL.LVE_MODE = 0;
11. Switch back hybrid oscillator to 32MHz frequency.
a. FW to set CCU_SYS_CLK_CTL.CCU_SYS_CLK_DIV to needed divisor
value.
b. FW configures Hybrid Oscillator (OSC0_CFG0/1 registers) to 32 MHz
Silicon oscillator mode while applying trimcode specific to 32 MHz
frequency.
12. Firmware can enable the needed components such as ADC, comparators,
peripheral subsystem to put the SoC into ACTIVE/Normal mode of operation
including enabling PERIPH_CLK_EN to 1’b1.
a. Note that none of the resets (say WARM_RST#) is asserted during
power state transitions.
b. since host processor subsystem is never powered down in low power
state, state of the CPU core as well as other SoC components are
preserved. Hence FW/OS is not expected to do a save/restore
operation, thus saving time in exit latency.
9.2 Power Down Sequences
Power down sequence is totally executed by FW depending on the low power state to
enter. PMU does not play any part in this sequence. Before entering low power state,
the intended wake sources have to be enabled.
The possible wake sources/events that can be configured by FW/SW while entering a
low power state is as below. Corresponding WAKE_MASK[31:0] and/or
CCU_LP_CLK_CTL.WAKE_PROBE_MODE_MASK register bits specific to the wake
source of interest has to be unmasked (set to 0) while remaining bits are to be
masked (set to 1) to prevent unwanted wake.