Datasheet

Power Up and Reset Sequence
Intel
®
Quark™ microcontroller D2000
January 2016 Datasheet
Document Number: 333577-002EN 77
4. PMU generates a strobe on VSEL_STROBE to RAR to put it in eSR mode at
1.8V VSEL_IN. Pulse width of VSEL_STROBE is based on
PM_WAIT.VSTRB_WAIT register. At the positive edge of VSEL_STROBE, RAR
deasserts ROK_BUF_VREG (if it is enabled/selected by VR_EN input).
a. When RAR is power recycled, RAR will default to eSR 1.8V mode
automatically. However at other times of RST_N, RAR may be in other
mode (for example, qLR Linear Regulator and non 1.8V). Hence this
strobing is done by PMU to get it predictably back to eSR 1.8V
regulation mode.
5. PMU waits for ROK_BUF_VREG from RAR to be asserted so that voltage
regulator (VR) has attained regulation. In case RAR VR is bypassed by VR_EN
input pin, RAR VR keeps ROK_BUF_VREG asserted always.
6. COLD_RST# and WARM_RST# are released. Clocks to LMT Processor, Memory
Subsystem (SRAM and Flash) are active.
7. Host processor LMT starts to execute from reset vector. Later on, Firmware
can enable the needed components such as ADC, comparators, peripheral
subsystem to put the SoC into ACTIVE/Normal mode of operation.
9.1.2 Low Power State to Active
For those low power states not requiring voltage regulator to be put into retention
(linear regulator) mode, below sequences are not required and can be handled by
SW/FW by powering up needed components based on System Power State. Below
sequence is applicable when voltage regulator was earlier put into retention/linear
regulator mode with core output voltage set to either 1.8V or lower (say 1.35V).
When the SoC is in any of Sleep states and a wake event is triggered, the following
sequence occurs:
1. An enabled wake event is triggered and latched within the SoC
2. The RTC Power Down input is asynchronously de-asserted by PMU in order to
restart the 32 kHz clock
a. Powering down the RTC oscillator is an optional step when entering
sleep (say DEEPSLEEP_NORTC state).
3. Hybrid Oscillator Power Down input is asynchronously deasserted by PMU.
Hybrid oscillator will come up in the same settings as it were at the time of
entering low power state.
4. Based on CCU_SYS_CLK_CTL.CCU_SYS_CLK_SEL programmed by FW at the
time of entering into low power state, sys_clk will take either Hybrid oscillator
output or RTC clock output. This step exits based on the LOCK time of selected
oscillator. If CCU_LP_CLK_CTL.CCU_EXIT_TO_HYBOSC was set to 1’b1, then
PMU ensures that sys_clk takes hybrid oscillator output.
5. Once the sys_clk starts ticking, Host Processor will get the wake interrupt.
LMT starts to execute.
6. FW to restore clock settings for normal mode: OSC0_PD=0, OSC1_PD=0 or 1
(1’b1 if RTCOSC is not needed in active state), CCU_SYS_CLK_SEL = 1
(HYBOSC) to be updated to proper values.
7. FW to program HYB_OSC_PD_LATCH_EN = 1, RTC_OSC_PD_LATCH_EN=1 so
that OSC0_PD and OSC1_PD values directly control the oscillators in active
state.
8. FW to make WAKE_MASK[31:0] to all-ones (all wake disabled) so that any
future interrupt in active power state does not interfere with wake related
logic (such as powering down oscillators etc).