Datasheet

Power Up and Reset Sequence
Intel
®
Quark™ microcontroller D2000
Datasheet January 2016
76 Document Number: 333577-002EN
9 Power Up and Reset Sequence
This chapter provides information on the following topics:
• Power Up Sequences
• Power Down Sequences
• Reset Behavior
9.1 Power Up Sequences
There are two cases of power up:
a. RST_N triggered Power Up (Any state to ACTIVE state). Covers Power
recycling.
b. From any Low Power State to ACTIVE state (based on any of configured wake
events)
Hardware (PMU) supports enabling on-die RAR Voltage Regulator. Hybrid Oscillator
and RTC Oscillator during the power up sequence. Rest of the SOC components are to
be enabled back by FW.
9.1.1 RST_N Triggered Transition to ACTIVE state
When RST_N is asserted following PVDD power cycle or otherwise, the following power
up sequence occurs:
1. RST_N is asserted by platform. This covers the case of Power recycle as well.
RST_N is kept asserted till PVDD input rail is within the operating range [2.0v-
3.6v]. SoC asserts POR_RST#, COLD_RST#, WARM_RST#. RST_N is to be
kept asserted for tROK_PROG (~250 usec; TBC) irrespective of whether
internal voltage regulator is enabled or disabled.
a. On-die RAR voltage regulator (VR) executes its powers up sequence
whenever PVDD recycles. At other times of RST_N assertion, RAR
Voltage regulator is not affected. If power cycled, RAR starts to
regulate in eSR Switching Regulator mode with 1.8V voltage output.
b. Hardware enables Hybrid Oscillator and RTC Oscillator. This is based
on the default values of OSC0_CFG0/1 and OSC1_CFG registers.
Hybrid oscillator is enabled in 4 MHz Silicon Oscillator mode with
default TRIM code of 0. At this stage, there is no expectation to have
2% accurate oscillator output but just to have clock cycles for starting
operation. Actual trimcode based on trimming is applied by FW later
based on trimcode stored in Flash. Oscillators will start of oscillate
once DVDD is stable above 1.62V.
2. RST_N is deasserted by platform. RST_N is expected to be asserted for
tROK_PROG (250 usec; TBC) to account for internal regulator startup time.
POR_RST# is removed.
3. RAR Voltage Regulator is set to eSR Switching Regulator mode with 1.8V
Voltage select. This is ensured by the default values of AON_VR register.