Datasheet

Power Management
Intel
®
Quark™ microcontroller D2000
January 2016 Datasheet
Document Number: 333577-002EN 75
8.4.2 External Voltage Regulator
Internal voltage regulator is disabled by grounding VREN to GND. In this case, DVDD
voltage input is supplied by an external voltage regulator. Here DVDD has to be
applied before IOVDD.
1. PVDD/AVDD/DVDD are applied together.
2. Wait for DVDD rail to ramp-up to stable regulated value.
3. As DVDD is stable, Hybrid oscillator starts oscillating in Silicon RC oscillator
mode outputting 4MHz +/- 40% (trimcode is not applied at this stage).
HYBOSC takes 2 usec for lock time.
4. After 50 usec minimum time, apply IOVDD rail. This is done to ensure that
there is no crowbar current between VDDPST (IOVDD) and VDDcore (DVDD)
in the level shifter inside digital IO Pads.
5. Internal voltage regulator provides a 0.95v +/- 15% internal reference voltage
to the RST_N comparator within 2 msec. Till reference voltage is stable,
voltage regulator sends an output to keep the RST_N comparator disabled
(output = 0), thus keeping SoC under reset (internal power-on reset).
6. Once external RST_N input is deasserted and RST_N is internally enabled, SoC
comes out of reset.
7. Processor is output of reset and fetches instruction at reset vector from flash.
After some steps, firmware will apply the actual trimcode to HYBOSC at
selected output frequency to get HYBOSC output to +/-2% accuracy.