Datasheet

Power Management
Intel
®
Quark™ microcontroller D2000
Datasheet January 2016
74 Document Number: 333577-002EN
8.4 Power Management Unit (PMU)
8.4.1 Internal Voltage Regulator
Internal voltage regulator is enabled by pulling high VREN to PVDD.
1. PVDD/AVDD/IOVDD are applied together. All these rails are from same
source.
2. After 240 usec of start-up time, Voltage regulator achieves regulated 1.8V
DVDD in switching voltage regulator mode.
a. Till DVDD is stable, Power-on control (POC) of IO pads is kept asserted
by an output (ROK_AVDB) from voltage regulator so that the level
shifter inside IO pad between VDDPST and VDDcore is dis-engaged.
3. When DVDD is stable, Hybrid oscillator starts oscillating in Silicon RC oscillator
mode outputting 4MHz +/- 40% (trimcode is not applied at this stage).
HYBOSC takes 2 usec for lock time.
4. Internal voltage regulator provides a 0.95v +/- 15% internal reference voltage
to the RST_N comparator within 2 msec. Till reference voltage is stable,
voltage regulator sends an output to keep the RST_N comparator disabled
(output = 0), thus keeping SoC under reset (internal power-on reset).
5. Once external RST_N input is deasserted and RST_N is internally enabled, SoC
comes out of reset.
6. Processor is output of reset and fetches instruction at reset vector from flash.
After some steps, firmware will apply the actual trimcode to HYBOSC at
selected output frequency to get HYBOSC output to +/-2% accuracy.