Datasheet

Power Management
Intel
®
Quark™ microcontroller D2000
January 2016 Datasheet
Document Number: 333577-002EN 73
The Intel
®
Quark™ microcontroller D2000 power architecture is given in Figure 6 and
uses a Retention Alternating Regulator (RAR). RAR works in two modes – normal
mode wherein Switching Regulator is turned on sourcing 50 mA of max current and
retention mode wherein linear regulator is turned on sourcing only 300 uA of max
current.
The entire SoC core is under single power domain (1.8v regulated output rail from
RAR) and is never power gated. Power saving is achieved by clock gating of logic and
also putting the hard macros (such as ADC, comparators, oscillators, voltage
regulator) in power down mode.
Tank capacitor at the output of LX is provided to ensure smooth switchover (no drop
or droop) from Linear Regulator (retention mode) to Switching Regulator (normal
mode) or vice-versa, provided current draw is restricted at less than 300 uA before
transition. Follow the integration guidelines from Dolphin and also review the backend
implementation with IP vendor.
Additionally in retention mode, RAR can supply only 300 uA of max current. Since the
SoC is in single power domain fed by 1.8v regulated output from RAR, FW/SW has to
ensure that enough components/devices are put into low power states such that
overall current draw is less than 300 uA in LOW POWER WAIT / DEEP SLEEP states.
No fail-safe scheme is implemented in the SoC.
VR_ROK_AVDB drives the POC rail of the I/O ring shutting down the I/O level shifters
to prevent damage while the DVDD supply comes into regulation.
Implementation may choose to separate Analog GND (RAR, ADC, Comparators) and
Digital GND (Std cells, Digital IO pads, memories, Oscillators) as separate pads and
ground it to VSS plane in package. Similarly vrefp and agndref ports of ADC can be
implemented as separate pads and bonded to AVDD and VSS respectively in package.
RST_N input uses low power comparator which has PVDD, AVDD and GND ports which
are to be connected to PVDD, AVDD and VSS inputs respectively. REF1 port of RST_N
comparator is connected to VREF_OUT from RAR.
Notes:
1. Current scheme assumes 40 ball QFN thus all digital and analog grounds are
routed to the QFN ground pad.
2. Current scheme assumes 40 ball QFN thus several power rails are ganged
together (e.g. ADC & Comparator).
3. ADC:
a. VREFP is double bonded to AVDD
b. AGNDREF is double boned to VSS
c. ADC Block has an internal LDO to create a clean 1.8V rail, DVDD_LDO
is provided to allow bypassing of the LDO.