Datasheet

Power Management
Intel
®
Quark™ microcontroller D2000
January 2016 Datasheet
Document Number: 333577-002EN 71
8.2.4 Minimum Voltage Limits (Vmin)
Table 23. Minimum Voltage Limits
Component
Condition
PVDD/IOVDD/
AVDD
DVDD
Min Max Min Max
RAR Voltage
Regulator
Normal
operation
1.62 V 3.63 V 1.08 V 3.63 V
ADC Normal or
Power Down
1.62 V 3.6 V 1.62 V 1.98 V
Comparator Normal or
Power Down
2.0 V 3.63 V 1.2 V 1.98 V
SRAM Normal
operation
- - 1.2 V 1.98 V
Flash Normal
operation
- - 1.2 V 1.98 V
Digital IO
pads
Normal
operation
- - 1.62 V 1.98 V
Hybrid
Oscillator (32
MHz)
Normal
operation
- - 1.62 V 1.98 V
Retention mode
(HYB_SET_REG
1[0]=1). 4 MHz
Si osc clock
output
- - 1.08 V 1.32 V
RTC Oscillator Normal
operation
1.5 V 3.63 V 1.1 V 3.63 V
Digital logic
(std cells)
Normal
operation
- - 1.2 V 1.98 V
Table 23 shows that DVDD has to be at 1.8V during normal operation. PVDD range is 2.0V
to 3.63V limited by comparator. DVDD during retention has to be 1.8V if IOs are needed to
be functional and can go below up to 1.2V (1.35V at RAR) if IOs are disabled/floating and
provided Flash can work at that level (TBC Check with TSMC). POR is only 1.8V DVDD
during retention.