Datasheet
Introduction
Intel
®
Quark™ microcontroller D2000
January 2016 Datasheet
Document Number: 333577-002EN 7
13.3.1.28 Enable (IC_ENABLE) ............................................... 175
13.3.1.29 Status (IC_STATUS) ................................................ 177
13.3.1.30 Transmit FIFO Level (IC_TXFLR) ............................... 179
13.3.1.31 Receive FIFO Level (IC_RXFLR) ................................. 179
13.3.1.32 SDA Hold (IC_SDA_HOLD) ....................................... 180
13.3.1.33 Transmit Abort Source (IC_TX_ABRT_SOURCE) ........... 180
13.3.1.34 SDA Setup (IC_DMA_CR) ......................................... 184
13.3.1.35 DMA Transmit Data Level Register (IC_DMA_TDLR) ..... 185
13.3.1.36 I2C Receive Data Level Register (IC_DMA_RDLR) ........ 185
13.3.1.37 SDA Setup (IC_SDA_SETUP) .................................... 186
13.3.1.38 General Call Ack (IC_ACK_GENERAL_CALL) ................ 187
13.3.1.39 Enable Status (IC_ENABLE_STATUS) ......................... 187
13.3.1.40 SS and FS Spike Suppression Limit (IC_FS_SPKLEN) ... 189
13.3.1.41 HS spike suppression limit (IC_HS_SPKLEN) ............... 190
13.3.1.42 Clear the RESTART_DET interrupt
(IC_CLR_RESTART_DET) ......................................... 191
13.3.1.43 Configuration Parameters (IC_COMP_PARAM_1) .......... 191
13.3.1.44 Component Version (IC_COMP_VERSION) .................. 191
13.3.1.45 Component Type (IC_COMP_TYPE) ............................ 192
14 UART .......................................................................................................... 193
14.1 Signal Descriptions ............................................................................. 193
14.2 Features ........................................................................................... 194
14.3 Memory Mapped IO Registers ............................................................... 195
14.3.1.1 Receive Buffer / Transmit Holding / Divisor Latch Low
(RBR_THR_DLL) ..................................................... 196
14.3.1.2 Interrupt Enable / Divisor Latch High (IER_DLH) ......... 198
14.3.1.3 Interrupt Identification / FIFO Control (IIR_FCR) ......... 199
14.3.1.4 Line Control (LCR) .................................................. 202
14.3.1.5 MODEM Control (MCR) ............................................. 204
14.3.1.6 Line Status (LSR) ................................................... 206
14.3.1.7 MODEM Status (MSR) .............................................. 211
14.3.1.8 Scratchpad (SCR) ................................................... 214
14.3.1.9 UART Status (USR) ................................................. 215
14.3.1.10 Halt Transmission (HTX) .......................................... 216
14.3.1.11 DMA Software Acknowledge (DMASA) ........................ 217
14.3.1.12 Transceiver Control Register (TCR) ............................ 217
14.3.1.13 Driver Output Enable Register (DE_EN) ...................... 219
14.3.1.14 Receiver Output Enable Register (RE_EN) ................... 220
14.3.1.15 Driver Output Enable Timing Register (DET) ............... 220
14.3.1.16 TurnAround Timing Register (TAT) ............................ 221
14.3.1.17 Divisor Latch Fraction (DLF) ..................................... 222
14.3.1.18 Receive Address Register (RAR) ................................ 222
14.3.1.19 Transmit Address Register (TAR) ............................... 223
14.3.1.20 Line Extended Control Register (LCR_EXT) ................. 224
15 SPI ............................................................................................................. 227
15.1 Signal Descriptions ............................................................................. 227
15.2 Features ........................................................................................... 228
15.3 Memory Mapped IO Registers ............................................................... 229
15.3.1.1 Control Register 0 (CTRLR0) ..................................... 231
15.3.1.2 Control Register 1 (CTRLR1) ..................................... 235
15.3.1.3 SSI Enable Register (SSIENR) .................................. 236
15.3.1.4 Microwire Control Register (MWCR) ........................... 236