Datasheet

Power Management
Intel
®
Quark™ microcontroller D2000
January 2016 Datasheet
Document Number: 333577-002EN 69
8.2.2 System Power State Definition
The Power Management states supported by the SoC are described in this section.
Table 21. SoC Power States
State Sub State Description
ACTIVE RUN Main supply rail is present and voltage regulator is in
regulation in Normal mode. System clock is running from
4MHz up to 32MHz. Processor in C0. FW has full control of
which peripherals to enable.
LOW POWER
COMPUTE
Main supply rail is present and voltage regulator is in
regulation in Normal mode. System clock is running at
less than 4MHz. Processor in C0. FW has full control of
which peripherals to enable.
HALT - Main supply rail is present and voltage regulator is in
regulation in Normal mode.
FW executes the HLT instruction to enter C2. FW has full
control of which peripherals to leave enabled when
entering C2.
Any enabled peripheral capable of generating an interrupt
can trigger an exit from HALT to ACTIVE
DEEP SLEEP
RTC
1.8V/1.35V
1.8V retention
Main supply rail is present and voltage regulator is in
regulation in Retention mode (Linear Regulator Mode
either 1.8V or 1.35V voltage output).
FW has put most of the SoC components (Hybrid
Oscillator, ADC, most comparators) in power down mode.
FW executes the HLT instruction to enter C2. RTC
oscillator is enabled.
All peripherals are disabled except for AON Periodic Timer,
RTC, GPIO and/or Comparator(s) which provide the wake
event from DEEP SLEEP to ACTIVE.
1.35V
retention
DEEP SLEEP
NO RTC
1.8V/1.35V
1.8V retention
Main supply rail is present and voltage regulator is in
regulation in Retention mode (Linear Regulator Mode
either 1.8V or 1.35V voltage output).
FW has put most of the SoC components (Hybrid
Oscillator, ADC, most comparators) in power down mode.
FW executes the HLT instruction to enter C2. RTC
oscillator is also powered down. RTC alarm, AON Periodic
timer are not available in this state. GPIO debouncing
cannot be done in this state. GPIO edge triggered
interrupt is not available as wake source as all clocks are
gated off in this state.
All peripherals are disabled except for GPIO level interrupt
or Comparator(s) which provide the wake event from
DEEP SLEEP to ACTIVE.
1.35V
retention