Datasheet

Power Management
Intel
®
Quark™ microcontroller D2000
January 2016 Datasheet
Document Number: 333577-002EN 67
Power State Definition Max
Current
Entry
Latency
Exit
Latency
How
Triggered
STBY Power Reduction mode
(stand-by). this mode
corresponds to a memory
that cannot perform any
read (or write) operation.
This mode is activated by
a CSN at high level at the
rising edge of CK.
- 0 0 Chip Select
CSN=H to
SRAM
deasserted
in a clock
cycle for
write or
read
operation
There is no specific control to put the SRAM into above power states.The Intel
®
Quark™ microcontroller D2000 has a single always-on power domain (DVDD) and
hence SRAM is always powered. SRAM state is always preserved. No special retention
mode is required. STBY state is entered automatically by SRAM when the chip select
to SRAM is inactive in a given clock cycle.
8.1.8 Peripherals
Table 20. Peripheral Power States
Power
State
Definitio
n
Max
Current
Entry
Latenc
y
Exit
Latenc
y
How Triggered
ON Peripheral
is enabled
retaining
internal
state and
clock to it
is running
Dynamic
current of
logic with
dependenc
y on
activity
factor.
1 cycle 1 cycle Setting respective bit in
CCU_PERIPH_CLK_GATE_C
TL register
STBY Peripheral
is enabled
retaining
internal
state but
clock to it
is gated.
Leakage
current of
logic
1 cycle 1 cycle Resetting respective bit in
CCU_PERIPH_CLK_GATE_C
TL register