Datasheet

Power Management
Intel
®
Quark™ microcontroller D2000
Datasheet January 2016
64 Document Number: 333577-002EN
8.1.3 ADC
Table 15. ADC Power States
Power State Definition Max
Current
Entry
Latency
Exit
Latency
How
Triggered
ON Normal Operation.
ADC is enabled for
conversation with
optionally enabled
internal LDO.
Enadc=H, enldo=H,
dislvl=L. powerup
time: 3-5-10 usec
(min-typ-max).
1000 uA
@ avdd,
100 uA
@ dvdd
at 5
MSps
- - Writing to
ADC_OP_MODE
register
STBY Standby Mode. ADC
is disabled but ADC
state is kept enabled
by enabling internal
LDO and retaining
DVDD. Enadc=L,
enldo=H, dislvl=L.
Exit involves 1
conversion cycle.
15 uA @
avdd, 1
uA @
dvdd
- 14 CLK
cycles
Writing to
ADC_OP_MODE
register
PD Power Down mode.
ADC is disabled,
calibration state is
retained, DVDD is
present, internal LDO
is off. Enadc=L,
enldo=L, dislvl=L. A
calibrated conversion
cycle can start
immediately after
internal LDO Power
Up time.
1 uA @
avdd, 1
uA @
dvdd
- 10 usec Writing to
ADC_OP_MODE
register
DPD Deep Power Down
mode. ADC is
disabled, calibration
state is lost, DVDD
can be off. Enadc=L,
enldo=L, dislvl=H.
exit involves waiting
for internal voltage
regulator to start-up
+ recalibration +
dummy conversion
cycle. A complete
calibration cycle lasts
81 clock cycles. A
conversion cycle is
14 CLK cycles for 12-
bit resolution.
1 uA @
avdd,
0.5 uA
@ dvdd
- 10 usec
+ 95
CLK
cycles.
Writing to
ADC_OP_MODE
register