Datasheet

Power Management
Intel
®
Quark™ microcontroller D2000
January 2016 Datasheet
Document Number: 333577-002EN 63
“OFF” power state is entered only when internal regulator is disabled using VREN=L
input pin and 1.8v rail (DVDD input) is fed directly from platform.
Voltage regulator in eSR mode has 90% efficiency down to 0.2 Imax (1 mA) and 70%
efficiency down to 0.01 Imax (500 uA). In iLR mode, power consumption of VR is
about 1% of delivered current.
The SoC power delivery is described in detail in the Power Architecture section.
8.1.2 CPU
Table 14. CPU Power States
Power
State
Definition Max
Curre
nt
Entry
Latenc
y
Exit
Latenc
y
How Triggered
C0 Active State
Processor executing
code
~5 mA
@
32MHz
3 cycles 6 cycles Any enabled
Interrupt event or
reset event
C2 Stop Clock / Halt
State
Entered via HLT
instruction
Exited via Interrupt
or Reset
Clock to LMT core
including Local APIC
and IO APIC is
gated. Clock to
memory subsystem
(SRAM and FLASH)
can also be gated if
CCU_MEM_HALT_EN
=1.
~50 nA 6 cycles 3 cycles CPU executing HLT
instruction provided
CCU_CPU_HALT_EN
=1
Processor in SoC does not support STOPCLK (for entering C2 state) but instead
executing HALT instruction is used to enter C2 state wherein clock to processor core
including LAPIC and IOAPIC is gated. The clock to LMT core can be gated after min 6
core clk cycles from xhalt detection (number of clock cycles is configurable and default
set to 16 clock cycles). In Intel
®
Quark™ microcontroller D2000, processor is never
power gated but only clock gated and hence processor state is always preserved.
Clock is re-enabled to the processor if there is any wake event or any enabled
interrupt.