Datasheet

Power Management
Intel
®
Quark™ microcontroller D2000
January 2016 Datasheet
Document Number: 333577-002EN 61
8 Power Management
This chapter provides information on the power management and power architecture
of the SoC.
Power architecture of SoC is based on the following premise:
1. There is no requirement to supply regulated voltage (1.8v or 3.3v) to platform
components from SoC.
a. This dictates the max current specification of internal voltage regulator
in the SoC.
2. Platform Components and SoC would operate from same battery source (eg
coincell).
a. The IOs of SoC and the Analog components would be on the same rail
as input battery source. Thus the electrical characteristics of SoC IOs
(digital or analog) would be a function of battery rail and not regulated
1.8v/3.3v.
3. SoC has to generate a regulated 1.8v supply (DVDD) from battery input for
operating its core logic.
a. There is level shifter in IOs between core voltage rail and IO rail
(IOVDD). Similarly analog components such as ADC and Comparators
take care of shifting from analog rail (AVDD) to core/digital rail or
vice-versa.
SoC has 4 power input pins:
1. PVDD – Used by internal voltage regulator only.
2. IOVDD – Used by digital IO pads. Electrical characteristics of all external
digital pins will be with respect to IOVDD.
3. AVDD – Used by Analog components such as ADC and Comparators. Electrical
characteristics of all external analog pins will be with respect to AVDD.
4. DVDD – Used as SoC Core Voltage. Normal mode operating point is 1.8V. It
can be fed either by internal voltage regulator’s output (to be circled back in
board); or from another regulated power supply from platform if internal
voltage regulator is disabled. All of SoC internals will operate with DVDD.
PVDD, IOVDD, AVDD can be from the same power source with noise isolation, or can
be independently supplied.
Power management of SoC is a function of how the individual component/device
power state is managed. The various components in SoC that play a role in power
management are Voltage Regulator, 32 MHz Oscillator, 32 kHz Oscillator, ADC, Analog
Comparators, memories (SRAM, Flash), Processor Core, Peripheral controllers (digital
logic) and IOs. Hence this chapter begins with a discussion on component power
states and then moves on to create System power states based on component power
states. The System power states are defined based on current draw requirement and
latencies involved in entering or exiting a given power state. System power state is
managed in Firmware/Software and not in hardware.