Datasheet

Clocking
Intel
®
Quark™ microcontroller D2000
Datasheet January 2016
60 Document Number: 333577-002EN
7.2.4.2 Flash DFS requirements
When using DFS on the root fabric clock the flash wait states must be adjusted for
both Flash instances. Refer to Memory Subsystem chapter for further details.
7.2.5 Dynamic Clock Gating
The Intel
®
Quark™ microcontroller D2000 supports a wide range of clock gating
options
1) Each leaf clock can be dynamically gated by firmware
To apply a DCG the following procedure should be used.
1) Write ‘0’ to the clock gate register CCU_XXX_PCLK_EN
2) The following hardware clock gating options are supported
a. UART low power autonomous hardware clock gating
b. SPI low power autonomous hardware clock gating
7.2.5.1 UART autonomous clock gating (ACG)
Both UART controllers support ACG mode (CCU_UARTX_PCLK_EN_SW=0). ACG is
asserted when the following occurs
1) Transmit and receive pipeline is clear (no data in the RBR/THR or TX/RX FIFO)
2) No activity has occurred on the SIN/SOUT lines
3) Modem input signals have not changed in more than one character time.
7.2.5.2 SPI autonomous clock gating (ACG)
All SPI controllers support ACG mode (CCU_SPI_XX_PCLK_EN_SW=0). ACG occurs
when the SSIENR register has been written to 0.