Datasheet
Introduction
Intel
®
Quark™ microcontroller D2000
Datasheet January 2016
6 Document Number: 333577-002EN
12.4.2.6 FLASH_STTS (FLASH_STTS) ..................................... 125
12.4.2.7 CTRL (CTRL) .......................................................... 126
12.4.2.8 FPR0_RD_CFG (FPR0_RD_CFG) ................................ 127
12.4.2.9 FPR1_RD_CFG (FPR1_RD_CFG) ................................ 128
12.4.2.10 FPR2_RD_CFG (FPR2_RD_CFG) ................................ 129
12.4.2.11 FPR3_RD_CFG (FPR3_RD_CFG) ................................ 130
12.4.2.12 MPR_WR_CFG (MPR_WR_CFG) ................................. 131
12.4.2.13 MPR_VSTS (MPR_VSTS) .......................................... 132
12.4.2.14 MPR_VDATA (MPR_VDATA) ...................................... 133
12.4.3 Internal SRAM Register Summary ............................................ 133
12.4.4 Internal SRAM Register Detailed Description .............................. 134
12.4.4.1 MPR_CFG (MPR0_CFG) ............................................ 134
12.4.4.2 MPR_CFG (MPR1_CFG) ............................................ 135
12.4.4.3 MPR_CFG (MPR2_CFG) ............................................ 136
12.4.4.4 MPR_CFG (MPR3_CFG) ............................................ 138
12.4.4.5 MPR_VDATA (MPR_VDATA) ...................................... 139
12.4.4.6 MPR_VSTS (MPR_VSTS) .......................................... 139
13 I
2
C .............................................................................................................. 141
13.1 Signal Descriptions ............................................................................. 141
13.2 Features ........................................................................................... 141
13.3 Memory Mapped IO Registers ............................................................... 142
13.3.1.1 Control Register (IC_CON) ....................................... 143
13.3.1.2 Master Target Address (IC_TAR) ............................... 146
13.3.1.3 Slave Address (IC_SAR) .......................................... 148
13.3.1.4 High Speed Master ID (IC_HS_MADDR) ..................... 149
13.3.1.5 Data Buffer and Command (IC_DATA_CMD) ............... 149
13.3.1.6 Standard Speed Clock SCL High Count
(IC_SS_SCL_HCNT) ................................................ 152
13.3.1.7 Standard Speed Clock SCL Low Count
(IC_SS_SCL_LCNT) ................................................. 153
13.3.1.8 Fast Speed Clock SCL High Count (IC_FS_SCL_HCNT) .. 153
13.3.1.9 Fast Speed I2C Clock SCL Low Count
(IC_FS_SCL_LCNT) ................................................. 154
13.3.1.10 High Speed I2C Clock SCL High Count
(IC_HS_SCL_HCNT) ................................................ 155
13.3.1.11 High Speed I2C Clock SCL Low Count
(IC_HS_SCL_LCNT) ................................................ 155
13.3.1.12 Interrupt Status (IC_INTR_STAT) .............................. 156
13.3.1.13 Interrupt Mask (IC_INTR_MASK) ............................... 160
13.3.1.14 Raw Interrupt Status (IC_RAW_INTR_STAT) ............... 164
13.3.1.15 Receive FIFO Threshold Level (IC_RX_TL) .................. 169
13.3.1.16 Transmit FIFO Threshold Level (IC_TX_TL) ................. 169
13.3.1.17 Clear Combined and Individual Interrupt
(IC_CLR_INTR) ...................................................... 170
13.3.1.18 Clear RX_UNDER Interrupt (IC_CLR_RX_UNDER) ........ 171
13.3.1.19 Clear RX_OVER Interrupt (IC_CLR_RX_OVER) ............. 171
13.3.1.20 Clear TX_OVER Interrupt (IC_CLR_TX_OVER) ............. 171
13.3.1.21 Clear RD_REQ Interrupt (IC_CLR_RD_REQ) ................ 172
13.3.1.22 Clear TX_ABRT Interrupt (IC_CLR_TX_ABRT) .............. 172
13.3.1.23 Clear RX_DONE Interrupt (IC_CLR_RX_DONE) ............ 173
13.3.1.24 Clear ACTIVITY Interrupt (IC_CLR_ACTIVITY) ............. 173
13.3.1.25 Clear STOP_DET Interrupt (IC_CLR_STOP_DET) .......... 174
13.3.1.26 Clear START_DET Interrupt (IC_CLR_START_DET) ...... 174
13.3.1.27 Clear GEN_CALL Interrupt (IC_CLR_GEN_CALL) .......... 175