Datasheet

Mapping Address Spaces
Intel
®
Quark™ microcontroller D2000
January 2016 Datasheet
Document Number: 333577-002EN 55
LMT clock is gated by HW autonomously based on HALT detection. It is ungated by
HW upon Interrupt assertion. There is an option to gate/ungate clock to Memory
subsystem too with LMT clock. Other than LMT and Memory subsystem clocks, for all
other functions, SW controls gate/ungate of their respective clocks.
6.2 SoC Fabric
The SoC Fabric is a multi-layer AHB fabric that provides interconnect between 2
Masters and 5 Slaves.
The two masters are LMT and DMA Controller – one on each AHB layer. The 5 slaves
are: DMA Controller, Flash, SRAM, SCSS and APB peripherals. The multi-layer fabric
allows multiple masters to access different slaves in parallel. When two or more
masters try to access the same slave simultaneously, the slave arbitrates between the
masters. With this topology, it is not possible for each master to access every slave
connected to the SoC fabric. The LMT master can access all the 5 slaves. DMA
Controller master can only access Flash Slave, SRAM Slave and APB Peripherals Slave.
Figure 5 Multi-Layer AHB fabric with ICM
LMT Master
DMA Controller Master
Flash Slave
SRAM Slave
DMA Controller Slave SCSS Slave
APB Peripherals Slave
2 Layer ICM
2 Layer ICM 2 Layer ICM
From an address decode perspective, DMA controller can target all destinations inside
Flash subsystem (Flash Configuration registers, Instruction Flash, 8KB OTP, 4KB OTP)
and all destinations inside SRAM subsystem (SRAM and SRAM Configuration
registers).
The Multi-layer AHB fabric also makes use of the HMASTER port on two ICM
components ICM_SRAM and ICM_FLASH. The HMASTER port on these two ICMs is
used by the slave for memory protection of the SRAM and Flash slaves. Each
HMASTER port for each layer on the ICM has a different ID code, this allows the slave
to identify which master is currently trying to access memory.