Datasheet

Mapping Address Spaces
Intel
®
Quark™ microcontroller D2000
January 2016 Datasheet
Document Number: 333577-002EN 53
6 Mapping Address Spaces
The SoC supports a single flat Memory address space. The SoC does not support IO
Address Space, PCI Configuration Space or Message Bus Space.
The Lakemont Processor core (LMT) can directly access memory space either through
code fetches over ITCM or data fetches over DTCM or through memory reads and
writes over AHB fabric.
This chapter describes how memory space is mapped to interfaces and peripherals in
the SoC.
6.1 Physical Address Space Mappings
Processor supports 32b addressing. There are 4 GB (32-bits) of physical address
space that can be used as:
• Memory Mapped I/O (MMIO – I/O fabric)
• Physical Memory (System Flash/System SRAM)
The LMT can access the full physical address space. DMA Controller, the only other
master agent on AHB fabric, can only access regions of physical address space allowed
via the multi-layer SoC fabric – see more details under SoC Fabric section.
All SoC peripherals map their registers and memory to physical address space. This
chapter summarizes the possible mappings.
6.1.1 SoC Memory Map
The SoC Memory Map is divided up as follows:
• Processor Local APIC (LAPIC)
• I/O APIC
• SoC Configuration registers
• SoC Peripherals
• System Flash (Flash and ROM – implemented as 2 distinct regions of OTP)
• System SRAM (Internal)
The LMT reset vector at 150h is located in OTP Code region of Intel
®
Quark™
microcontroller D2000. System addresses 0xFFFF_FFF0 and 0xFFFF_FFF8 are a special
case by LMT and get aliased to reset vector.