Datasheet

Introduction
Intel
®
Quark™ microcontroller D2000
January 2016 Datasheet
Document Number: 333577-002EN 5
9.3 Reset Behavior.................................................................................... 83
9.3.1 Power On Reset ..................................................................... 84
9.3.2 Cold Reset............................................................................. 85
9.3.3 Warm Reset .......................................................................... 85
10 Thermal Management ..................................................................................... 87
10.1 Overview ........................................................................................... 87
11 Processor Core .............................................................................................. 88
11.1 Features ............................................................................................ 88
11.2 Processor Memory Map ........................................................................ 90
11.3 Main Fabric Bus Cycle Processing ........................................................... 92
11.3.1.1 Code Reads ............................................................ 92
11.3.1.2 Memory Reads and Memory Writes ............................. 92
11.3.1.3 IO Reads and IO Writes ............................................ 93
11.3.1.4 Interrupt Acknowledge ............................................. 93
11.3.1.5 Special Cycles ......................................................... 93
11.3.1.6 MSI ....................................................................... 95
11.3.1.7 End of Interrupt ...................................................... 95
11.3.2 Mapping FSB to AHB ............................................................... 95
11.3.2.1 Byte Enables ........................................................... 95
11.4 Intel
®
Quark™ microcontroller D2000 Interrupt Controller (MVIC) .............. 97
11.4.1 MVIC Registers ...................................................................... 98
11.4.1.1 TPR ....................................................................... 98
11.4.1.2 PPR ....................................................................... 98
11.4.1.3 EOI ........................................................................ 99
11.4.1.4 SIVR ...................................................................... 99
11.4.1.5 ISR ........................................................................ 99
11.4.1.6 IRR ....................................................................... 100
11.4.1.7 LVTTIMER .............................................................. 100
11.4.1.8 ICR ....................................................................... 101
11.4.1.9 CCR ...................................................................... 101
11.4.2 Programming Sequence ......................................................... 102
11.4.3 Interrupt Latency Reduction .................................................... 102
11.4.4 Sample Code ........................................................................ 104
11.5 CPUID .............................................................................................. 105
12 Memory Subsystem ....................................................................................... 106
12.1 Features ........................................................................................... 106
12.1.1 System Flash Controller Features ............................................. 106
12.1.2 OTP Features ........................................................................ 108
12.1.3 Internal SRAM Features .......................................................... 109
12.2 Error Handling ................................................................................... 111
12.3 Memory Consistency Analysis ............................................................... 114
12.3.1 Producer/Consumer Model Analysis of the Memory Subsystem ..... 117
12.3.2 Miscellaneous Memory Ordering related Scenarios ...................... 119
12.4 Memory Mapped IO Registers ............................................................... 120
12.4.1 Flash Controller 0 Register Summary ....................................... 120
12.4.2 Flash Controller 0 Register Detailed Description ......................... 121
12.4.2.1 TMG_CTRL (TMG_CTRL) .......................................... 121
12.4.2.2 ROM_WR_CTRL (ROM_WR_CTRL) ............................. 122
12.4.2.3 ROM_WR_DATA (ROM_WR_DATA) ............................ 123
12.4.2.4 FLASH_WR_CTRL (FLASH_WR_CTRL) ........................ 124
12.4.2.5 FLASH_WR_DATA (FLASH_WR_DATA) ....................... 125