Datasheet

Electrical Characteristics
Intel
®
Quark™ microcontroller D2000
January 2016 Datasheet
Document Number: 333577-002EN 49
Parameter Min Max
Hold time of SPI_M_RXD
with respect to SPI_M_SCLK
sampling edge
0 ns
-
Output load supported for SPI_M_TXD, SPI_M_SS[3:0], SPI_M_SCLK outputs is 25 pF
max to support max rate of 16 Mbps.
4.6.2 SPI Slave IO AC characteristics
SPI Slave interface consists of:
• Outputs SPI_S_SDOUT
• Inputs SPI_S_SCLK, SPI_S_SDIN, SPI_S_SCS
As per SPI protocol, the interface is timed with respect to SPI_S_SCLK which is input
to SoC. A given signal is launched with respect of a configured edge and sampled with
respect to the opposite edge. Thus it is a half-cycle setup/hold path.
Output load supported for SPI_S_SDOUT output is 50 pF max and 5 pF min.
Parameter Min Max
SPI Slave Clock SPI_S_CLK
Frequency
- 3.2 MHz (= 312.5 ns)
Setup time of
SPI_S_SDIN/SPI_S_SCS
with respect to sampling
edge of SPI_S_SCLK input
- 30 ns
Hold time of
SPI_S_SDIN/SPI_S_SCS
with respect to sampling
edge of SPI_S_SCLK input
- 120 ns
Output delay of
SPI_S_SDOUT with respect
to launching edge of
SPI_S_SCLK input
0 ns 120 ns
4.6.3 I
2
C Master/Slave IO AC characteristics
I
2
C interface consists of I2C_SCL and I2C_SDA bidirectional IOs and can operate in
either master or slave mode. It can operate in standard mode (with data rates 0 to 100
Kbps), fast mode (with data rates less than or equal to 400 Kbps) or fast mode plus
(with data rates less than or equal to 1 Mbps). To support fast mode plus, i2c_m0_clk
(= system clock) shall be greater than or equal to 32 MHz.
I
2
C specification dictates timing relationship between I2C_SCL and I2C_SDA to be
met, which will be broadly taken care by the I
2
C controller using configuration
registers. SoC complies with the timing and load capacitance given in I2C
specification.