Datasheet

Electrical Characteristics
Intel
®
Quark™ microcontroller D2000
Datasheet January 2016
48 Document Number: 333577-002EN
Scenario Condition Min Typ Max Unit
- CPU in C2 power
state (executed HALT
instruction)
- All peripherals clock
gated
- Hybrid Oscillator and
RTC Oscillator
powered down
- ADC and
Comparators powered
down.
- 1 GPIO input
enabled for level
sensitive interrupt
wake
- Internal Voltage
Regulator enabled in
Linear Regulator mode
(1.8V or 1.35V voltage
output)
Vpvdd=Vavdd=Viovdd=3.3V
Vdvdd = 1.35V,
-40≤T≤85
0
c
- 1.3 µA
4.6 AC Specifications
4.6.1 SPI Master IO AC characteristics
SPI Master interface consists of:
• Outputs SPI_M_SCLK, SPI_M_TXD, SPI_M_SS[3:0]
• Inputs SPI_M_RXD
The interface is timed with respect to SPI_M_SCLK which is output from SoC. A given
signal is launched with respect of a configured edge and sampled with respect to the
opposite edge. Thus it is a half-cycle setup/hold path.
Parameter Min Max
SPI Master Clock
SPI_M_SCLK frequency
-
16 MHz (= sysclk / 2).
Output delay for
SPI_M_SS[3:0]/SPI_M_TXD
with respect to SPI_M_SCLK
launch clock edge
0 ns
14 ns
Setup time of SPI_M_RXD
with respect to SPI_M_SCLK
sampling edge
15 ns
-