Datasheet

AON Counters
Intel
®
Quark™ microcontroller D2000
January 2016 Datasheet
Document Number: 333577-002EN 475
Before setting AONPT_RST register to 1, check if RTC OSC has attained lock and is
running. This is achieved by checking for non-zero value of AON Counter, which free-
runs on RTC clock if enabled.
The counter can the reset to the value contained in (AONPT_CFG) by writing to 1 to
(AONPT_RST). (AONPT_RST) is self-clearing however due to clock domain crossing of
register value from the slow to the fast domain, it needs to be polled to ensure the
reset has occurred.
1. Check if RTC Clock is running by polling for non-zero value on AON Counter. Wait
till AON Counter is non-zero (assumption is that AON Counter is already enabled
by AONC_CFG. AONC_CNT_EN = 1).
2. Write the timeout value to (AONPT_CFG) to stop the counter
3. Write 1 to (AONPT_RST) to apply the counter value.
4. Poll (AONPT_RST) till it clears to 0 to ensure the operation has complete.
5. At this time AONPT Counter in RTC Clock domain has started running.
AON Periodic Timer is running in RTC Clock domain. It will take 1 RTC clock cycle to
get reflected in AONPT_CNT read data. So AONPT_CNT read data value (in system
clock domain) at any time would be 1 RTC clock cycle old value of AONPT counter in
RTC clock domain.
Note step (3) can take a number of 32kHz clocks (1000’s of 32MHz clocks to
complete)
The sequence for clearing an interrupt should be as follows
1. Interrupt asserted
2. Write 0 to the (AONPT_CFG) to stop the counter
3. Write 1 to (AONPT_CLR) to clear the interrupt
4. Poll (AONPT_CLR) to ensure the operation has complete
Note step (3) can take a number of 32kHz clocks (1000’s of 32MHz clocks to
complete)
In addition, if both AON Counter and AON Periodic timer is not used, in order to
conserve power, the clocks to these block can be gated by
resetting CCU_LP_CLK_CTL.CCU_AON_TMR_CNT_CLK_EN_SW register bit to 0 in
SCSS.