Datasheet

System Control Subsystem
Intel
®
Quark™ microcontroller D2000
Datasheet January 2016
456 Document Number: 333577-002EN
24.3.1.57 Reset Status (RSTS)
MEM Offset (00000000) 574h
Security_PolicyGroup
IntelRsvd False
Size 32 bits
Default 0000_0000h
Bits Access
Type
Default Description PowerWel
l
ResetSigna
l
31:6 RO 26'h000000
0
RSVD (RSVD)
Reserved
5 RW/1C/V/
P
1'h0 Processor Bus Error
(BUS_ERR)
Status bit indicating
that an error response
has been observed on
the processor bus.
0b : No Bus Error
Response Observed
1b : Bus Error
Response Observed
4 RO 1'h0 RSVD (RSVD)
Reserved
3 RW/1C/V/
P
1'h0 Host Processor Halt
Interrupt Triggered
Warm Reset
(HOST_HALT_WRST
)
When this bit is set, it
indicates that an
enabled Host Halt
interrupt triggered a
warm reset.
2 RO 1'h0 RSVD (RSVD)
Reserved
1 RW/1C/V/
P
1'h0 Watchdog Timer
Triggered Warm
Reset (WDG_WRST)
When this bit is set, it
indicates that
Watchdog Timer in the
Peripheral block
triggered a warm
reset.