Datasheet

System Control Subsystem
Intel
®
Quark™ microcontroller D2000
Datasheet January 2016
454 Document Number: 333577-002EN
Bits Access
Type
Default Description PowerWell ResetSignal
2 RW/1C/V/P 1'h0 Processor Shutdown
(SHDWN)
Status bit indicating
the processor has
issued a Shutdown
special cycle.
A Shutdown special
cycle is generated
when the processor
incurs a double fault.
The processor remains
in Shutdown mode
until it is reset. This bit
is set when the
Shutdown special cycle
is issued and can only
be cleared by software.
0b : No Shutdown
Special Cycle Issued
1b : Shutdown Special
Cycle Issued
1 RO 1'h0 RSVD (RSVD)
Reserved
0 RW/1C/V/P 1'h0 Processor Halt (HLT)
Status bit indicating
the processor has
entered the Halt state.
When a HLT instruction
is executed, the
processor transitions
to the Halt state.
0b : Processor not in
Halt State
1b : Processor was in
Halt State
24.3.1.56 Reset Control (RSTC)
A write to this register with RSTC.COLD or RSTC.WARM set initiates a reset. Software
must only write to one of these bits at a time, else the behavior is undefined.
These bits automatically clear once the reset occurs, so there is no need for software
to clear them.
MEM Offset (00000000) 570h
Security_PolicyGroup
IntelRsvd False
Size 32 bits
Default 0000_0000h