Datasheet
System Control Subsystem
Intel
®
Quark™ microcontroller D2000
January 2016 Datasheet
Document Number: 333577-002EN 453
24.3.1.55 Processor Status (P_STS)
MEM Offset (00000000) 560h
Security_PolicyGroup
IntelRsvd False
Size 32 bits
Default 0000_0000h
Bits Access
Type
Default Description PowerWell ResetSignal
31:27 RO 5'h00 RSVD (RSVD)
Reserved
26 RW/P/L 1'h0 Halt Interrupt
Redirection
(HALT_INT_REDIR)
When an enabled host
halt interrupt occurs,
this bit determines if
the interrupt event
triggers a warm reset
or an entry into Probe
Mode.
0b : Warm Reset
1b : Probe Mode Entry
25:4 RO 22'h000000 RSVD (RSVD)
Reserved
3 RW/1C/V 1'h0 Processor Bus Error
Interrupt Status
(BUS_ERR)
Interrupt Status bit
indicating that an error
response has been
observed on the
processor bus.
0b : No Bus Error
Response Observed
1b : Bus Error
Response Observed, if
bus error is
programmed to cause
warm reset, this bit
gets
cleared at warm reset
otherwise software has
to clear this bit for this
interrupt clearing.