Datasheet

System Control Subsystem
Intel
®
Quark™ microcontroller D2000
January 2016 Datasheet
Document Number: 333577-002EN 423
Bits Access
Type
Default Description PowerWell ResetSignal
12 RW/1S 1'h0 OSC1 Powerdown Lock
(OSC1_PD_LOCK)
1b: Lock
pwr_rst_n
11 RW/1S 1'h0 OSC0 Powerdown Lock
(OSC0_PD_LOCK)
1b: Lock
pwr_rst_n
10:0 RO 11'h000 RSVD (RSVD)
Reserved
24.3.1.15 SoC Control Register (SOC_CTRL)
MEM Offset (00000000) 40h
Security_PolicyGroup
IntelRsvd False
Size 32 bits
Default 0000_0000h
Bits Access
Type
Default Description PowerWell ResetSignal
31:1 RO 31'h0000_000
0
RSVD (RSVD)
Reserved
0 RW/P/L 1'b0 Override OTP
Security
(OVR_OTP_SEC)
If 8KB OTP area is
OTPed, then JTAG
access to HVM tap, LMT
tap is not allowed (Intel
Orange access).
This is a lockable
register bit after cold
reset, which is written
by boot FW to override
OTP bit (On-time-
programmed bit in
Flash) based security
restrictions (example:
Disabling JTAG access
to Flash).
0b: Security restrictions
based on OTP bit is
enforced.
1b: Override OTP bit
based security
restrictions