Datasheet

System Control Subsystem
Intel
®
Quark™ microcontroller D2000
January 2016 Datasheet
Document Number: 333577-002EN 421
Bits Access
Type
Default Description PowerWell ResetSignal
2 RW/P/L 1'b1 RTC Clock Divider
Enable
(CCU_RTC_CLK_DIV_EN
)
This bit must be written
from 0 -> 1 to apply the
value
1 RW/P/L 1'b1 RTC Clock Enable
(CCU_RTC_CLK_EN)
1b: enable
0b: disable
0 RW/P 1'b1 Select Clock
(CCU_SYS_CLK_SEL)
0b: 32 kHz RTC Crystal
Oscillator
1b: 32 MHz Hybrid
Oscillator
24.3.1.14 Clocks Lock Register (OSC_LOCK_0)
MEM Offset (00000000) 3Ch
Security_PolicyGroup
IntelRsvd False
Size 32 bits
Default 0000_0000h
Bits Access
Type
Default Description PowerWell ResetSignal
31 RW/1S 1'h0 Test Mode Input 4 Lock
(OSC0_HYB_SET_REG4_LOC
K)
1b: Lock
pwr_rst_n
30 RW/1S 1'h0 Test Mode Input 3 Lock
(OSC0_HYB_SET_REG3_LOC
K)
1b: Lock
pwr_rst_n
29 RW/1S 1'h0 Test Mode Input 2 Lock
(OSC0_HYB_SET_REG2_LOC
K)
1b: Lock
pwr_rst_n
28 RW/1S 1'h0 Test Mode Input 1 Lock
(OSC0_HYB_SET_REG1_LOC
K)
1b: Lock
pwr_rst_n