Datasheet

System Control Subsystem
Intel
®
Quark™ microcontroller D2000
Datasheet January 2016
420 Document Number: 333577-002EN
24.3.1.13 System Clock Control Register (CCU_SYS_CLK_CTL)
MEM Offset (00000000) 38h
Security_PolicyGroup
IntelRsvd False
Size 32 bits
Default 0000_0087h
Bits Access
Type
Default Description PowerWell ResetSignal
31:11 RO 21'h0000
00
RSVD (RSVD)
Reserved
10:8 RW/P 3'h0 System Clock Divider
(CCU_SYS_CLK_DIV)
000b: divide by 1
001b: divide by 2
010b: divide by 4
011b: divide by 8
100b: divide by 16
101b: divide by 32
110b: divide by 64
111b: divide by 128
7 RW/P 1'b1 System Clock Divider
Enable
(CCU_SYS_CLK_DIV_EN
)
This bit must be written
from 0 -> 1 to apply the
value
6:3 RW/P/L 4'h0 RTC Clock Divider
(CCU_RTC_CLK_DIV)
0000b: divide by 1
0001b: divide by 2
0010b: divide by 4
0011b: divide by 8
0100b: divide by 16
0101b: divide by 32
0110b: divide by 64
0111b: divide by 128
1000b: divide by 256
1001b: divide by 512
1010b: divide by 1024
1011b: divide by 2048
1100b: divide by 4096
1101b: divide by 8192
1110b: divide by 16384
1111b: divide by 32768