Datasheet

System Control Subsystem
Intel
®
Quark™ microcontroller D2000
January 2016 Datasheet
Document Number: 333577-002EN 419
24.3.1.12 AHB Control Register (CCU_MLAYER_AHB_CTL)
MEM Offset (00000000) 34h
Security_PolicyGroup
IntelRsvd False
Size 32 bits
Default 0000_0014h
Bits Access
Type
Default Description PowerWell ResetSignal
31:7 RO 25'h000000
0
RSVD (RSVD)
Reserved
6 RW/P 1'b0 DMA Clock enable
(CCU_DMA_CLK_EN)
This controls clock to DMA
Controller. By default
clock to DMA controller is
disabled.
1b: enable
0b: disable
5 RO 1'h0 RSVD (RSVD)
Reserved
4 RW/P 1'b1 SRAM Clock Enable
(CCU_SRAM_CLK_EN)
1b: enable
0b: disable
3 RO 1'h0 RSVD (RSVD)
Reserved
2 RW/P 1'b1 FLASH 0 Clock Enable
(CCU_FLASH0_CLK_EN
)
1b: enable
0b: disable
1:0 RO 2'h0 RSVD (RSVD)
Reserved