Datasheet
System Control Subsystem
Intel
®
Quark™ microcontroller D2000
Datasheet January 2016
418 Document Number: 333577-002EN
24.3.1.11 Wake Mask register (WAKE_MASK)
MEM Offset (00000000) 30h
Security_PolicyGroup
IntelRsvd False
Size 32 bits
Default FFFF_FFFFh
Bits Access
Type
Default Description PowerWell ResetSignal
31:0 RW/P/L 32'hFFFFFFFF Wake Mask register
(WAKE_MASK)
Wake Mask Enable for
corresponding 32 irq
sources.
[31:19]: RESERVED
[18]:
FLASH_CONTROLLER_0
[17]: SRAM_CONTROllER
[16]: WATCHDOG
[15]: GPIO
[14]: COMPARATORS
[13]: DMA_CHANNEL_0
[12]: DMA_CHANNEL_1
[11]: TIMER
[10]: ADC_POWER
[9]: ADC_CALIBRATION
[8]: UART_0
[7]: SPI_MST_0
[6]: UART_1
[5]: SPI_SLV
[4]: I2C_MST_0
[3]: AON_TIMER
[2]: RTC
[1]: HOST_BUS_ERR
[0]: DMA_ERROR
If enabled, respective irq
source will act as the
wake source to exit from
low power state.
1b: Wake source is
Masked
0b: Wake source is
Enabled