Datasheet

System Control Subsystem
Intel
®
Quark™ microcontroller D2000
January 2016 Datasheet
Document Number: 333577-002EN 417
Bits Acces
s
Type
Defaul
t
Description PowerW
ell
ResetSign
al
12:8 RW/P 5'b1000
0
CCU CPU Halt Clock Count
(CCU_CPU_HALT_CLK_CNT)
This defines the number of clock
cycles clock can be gated
whenever cpu executes halt
instruction.
7:5 RO 3'h0 RSVD (RSVD)
Reserved
4 RW/P 1'b0 CCU LP Exit to Hybrid Oscillator
(CCU_EXIT_TO_HYBOSC)
This is provided to control the mux
between hybrid oscillator and RTC
oscillator for sys_clk at the time of
exiting low power state.
0b : No operation. sys_clk mux is
controlled by CCU_SYS_CLK_SEL.
1b : CCU_SYS_CLK_SEL is
overridden to select hybrid
oscillator at the time of low power
state exit when wake event occurs.
3 RW/P 1'b0 CCU Memory Subsystem Halt
Enable (CCU_MEM_HALT_EN)
This defines how the clock to the
Memory Subsystem (SRAM, Flash)
is controlled in SoC active state.
0b : Clock to SRAM & Flash are
controlled by respective SW clock
enables.
1b : Clock to SRAM & Flash runs
whenever the clock to host
processor is running. In this mode,
SW clock enables are ignored.
2 RW/P 1'b0 CCU CPU Halt Enable
(CCU_CPU_HALT_EN)
This defines how the clock to the
Host Processor Subsystem (CPU
core, Local APIC and IOAPIC) is
controlled in SoC active state.
0b : Host Processor Subsytem
clock is kept enabled irrespective
of halt execution.
1b : Host Processor Subsytem
clock is disabled when cpu
executes halt instuction. And is
reenabled when interrupt event
occurs.
1:0 RO 2'h0 RSVD (RSVD)
Reserved