Datasheet

System Control Subsystem
Intel
®
Quark™ microcontroller D2000
Datasheet January 2016
416 Document Number: 333577-002EN
24.3.1.10 System Low Power Clock Control (CCU_LP_CLK_CTL)
MEM Offset (00000000) 2Ch
Security_PolicyGroup
IntelRsvd False
Size 32 bits
Default 0001_F000h
Bits Acces
s
Type
Defaul
t
Description PowerW
ell
ResetSign
al
31:1
7
RO 15'h000
0
RSVD (RSVD)
Reserved
16 RW/P 1'b1 Clock gate Enable for AON_CNT
(CCU_AON_TMR_CNT_CLK_EN
_SW)
Clock gate Enable for AON_CNT.
1b: Clock is Enabled
0b: Clock is disabled
15 RW/P 1'b1 Latch Enable for the RTC Osc
PD Latch
(RTC_OSC_PD_LATCH_EN)
Latch Enable for the RTC Osc PD
Latch.
1b: OSC1_CFG0.OSC1_PD register
value is passed to RTC Osc
immediaetly
0b: OSC1_CFG0.OSC1_PD register
value is passed to RTC Osc only
when CPU is halted
14 RW/P 1'b1 Latch Enable for the Hybrid Osc
PD Latch
(HYB_OSC_PD_LATCH_EN)
Latch Enable for the Hybrid Osc PD
Latch.
1b: OSC0_CFG1.OSC0_PD register
value is passed to Hybrid Osc
immediaetly
0b: OSC0_CFG1.OSC0_PD register
value is passed to Hybrid Osc only
when CPU is halted
13 RW/P 1'b1 Wake Mask for Probe Mode
(WAKE_PROBE_MODE_MASK)
Wake Mask Enable for Probe Mode
irq source.
If enabled, probe mode irq source
will act as the wake source to exit
from low power state.
1b: Wake source is Masked
0b: Wake source is Enabled