Datasheet

System Control Subsystem
Intel
®
Quark™ microcontroller D2000
January 2016 Datasheet
Document Number: 333577-002EN 415
24.3.1.9 External Clock Control Register
(CCU_EXT_CLOCK_CTL)
MEM Offset (00000000) 24h
Security_PolicyGroup
IntelRsvd False
Size 32 bits
Default 0000_0007h
Bit
s
Acces
s Type
Default Description PowerWel
l
ResetSigna
l
31:5 RO 27'h000000
0
RSVD (RSVD)
Reserved
4:3 RW/P 2'h0 External clock divider
(CCU_EXT_CLK_DIV)
00b: divide by 1
01b: divide by 2
10b: divide by 4
11b: divide by 8
2 RW/P 1'b1 External clock divider
enable
(CCU_EXT_CLK_DIV_EN
)
This bit must be written
from 0 -> 1 to apply the
value
1 RW/P 1'b1 External Clock Enable
(CCU_EXT_CLK_EN)
1b: enable
0b: disable
0 RW/P 1'b1 External RTC enable
(CCU_EXT_RTC_EN)
1b: enable
0b: disable