Datasheet

System Control Subsystem
Intel
®
Quark™ microcontroller D2000
Datasheet January 2016
414 Document Number: 333577-002EN
24.3.1.8 Peripheral Clock Divider Control 1
(CCU_GPIO_DB_CLK_CTL)
MEM Offset (00000000) 20h
Security_PolicyGroup
IntelRsvd False
Size 32 bits
Default 0000_0003h
Bit
s
Acces
s
Type
Default Description PowerWe
ll
ResetSign
al
31:
5
RO 27'h000000
0
RSVD (RSVD)
Reserved
4:2 RW/P 3'h0 General Purpose IO
debounce clock divider
(CCU_GPIO_DB_CLK_DIV)
000b: divide by 1
001b: divide by 2
010b: divide by 4
011b: divide by 8
100b: divide by 16
101b: divide by 32
110b: divide by 64
111b: divide by 128
1 RW/P 1'b1 General Purpose IO
debounce clock divider
enable
(CCU_GPIO_DB_CLK_DIV_
EN)
This bit must be written from 0
-> 1 to apply the value
0 RW/P 1'b1 General Purpose IO
Debounce Clock Enable
(CCU_GPIO_DB_CLK_EN)
1b: enable
0b: disable