Datasheet

System Control Subsystem
Intel
®
Quark™ microcontroller D2000
January 2016 Datasheet
Document Number: 333577-002EN 413
Bits Access
Type
Default Description PowerWell ResetSignal
0 RW/P 1'b1 PERIPH_HCLK_EN
(CCU_PERIPH_HCLK_EN)
This controls the peripheral hclk
clock which is given to periph
icm & AHB2APB Bridge.
1b: enable
0b: disable
24.3.1.7 Peripheral Clock Divider Control 0
(CCU_PERIPH_CLK_DIV_CTL0)
MEM Offset (00000000) 1Ch
Security_PolicyGroup
IntelRsvd False
Size 32 bits
Default 0000_0001h
Bits Acces
s
Type
Default Description PowerWe
ll
ResetSign
al
31:2
6
RO 6'h00 RSVD (RSVD)
Reserved
25:1
6
RW/P 10'h0 ADC Clock divider (divisor is
N+1) (CCU_ADC_CLK_DIV)
0d: divide by 1
1d: divide by 2
2d: divide by 3
.....
1023d: divide by 1024
15:3 RO 13'h000
0
RSVD (RSVD)
Reserved
2:1 RW/P 2'h0 Peripheral Clock divider
(CCU_PERIPH_PCLK_DIV)
00b: divide by 1
01b: divide by 2
10b: divide by 4
11b: divide by 8
0 RW/P 1'b1 Peripheral Clock divider
enable
(CCU_PERIPH_PCLK_DIV_E
N)
This bit must be written from 0
-> 1 to apply the value