Datasheet

System Control Subsystem
Intel
®
Quark™ microcontroller D2000
Datasheet January 2016
412 Document Number: 333577-002EN
Bits Access
Type
Default Description PowerWell ResetSignal
10 RW/P 1'b1 Watch Dog Timer clock gate
enable
(CCU_WDT_PCLK_EN_SW)
1b: enable
0b: disable
9 RO 1'h0 RSVD (RSVD)
Reserved
8 RW/P 1'b1 General Purpose IO
Debounce Clock Enable
(CCU_PERIPH_GPIO_DB_CL
K_EN)
1b: enable
0b: disable
7 RW/P 1'b1 General Purpose IO
interrupt Clock Enable
(CCU_GPIO_INTR_CLK_EN)
1b: enable
0b: disable
6 RO 1'h0 RSVD (RSVD)
Reserved
5 RW/P 1'b1 SPI Master 0 clock enable
(CCU_SPI_M0_CLK_EN)
1b: enable
0b: disable
4 RW/P 1'b1 SPI Slave Clock Enable
(CCU_SPI_S_CLK_EN)
1b: enable
0b: disable
3 RO 1'h0 RSVD (RSVD)
Reserved
2 RW/P 1'b1 I2C Master 0 Clock enable
(CCU_I2C_M0_CLK_EN)
1b: enable
0b: disable
1 RW/P 1'b0 Peripheral clock enable
(CCU_PERIPH_CLK_EN)
This controls the peripheral
clock trunk. By default clocks to
peripheral Subsytem is disable.
1b: enable
0b: disable