Datasheet

System Control Subsystem
Intel
®
Quark™ microcontroller D2000
January 2016 Datasheet
Document Number: 333577-002EN 411
Bits Access
Type
Default Description PowerWell ResetSignal
21:2
0
RO 2'h0 RSVD (RSVD)
Reserved
19 RW/P 1'b1 I2C master 0 pclk clock gate
enable
(CCU_I2C_M0_PCLK_EN_S
W)
1b: enable
0b: disable
18 RW/P 1'b1 UART B pclk clock gate
enable
(CCU_UARTB_PCLK_EN_SW
)
1b: enable
0b: disable
17 RW/P 1'b1 UART A pclk clock gate
enable
(CCU_UARTA_PCLK_EN_SW
)
1b: enable
0b: disable
16 RW/P 1'b1 SPI slave pclk clock gate
enable
(CCU_SPI_PCLK_EN_SW)
1b: enable
0b: disable
15 RO 1'h0 RSVD (RSVD)
Reserved
14 RW/P 1'b1 SPI master 0 pclk clock gate
enable
(CCU_SPI_M0_PCLK_EN_S
W)
1b: enable
0b: disable
13 RW/P 1'b1 GPIO pclk clock gate enable
(CCU_GPIO_PCLK_EN_SW)
1b: enable
0b: disable
12 RW/P 1'b1 Timer pclk clock gate enable
(CCU_TIMER_PCLK_EN_SW)
1b: enable
0b: disable
11 RW/P 1'b1 RTC pclk clock gate enable
(CCU_RTC_PCLK_EN_SW)
1b: enable
0b: disable