Datasheet

System Control Subsystem
Intel
®
Quark™ microcontroller D2000
Datasheet January 2016
410 Document Number: 333577-002EN
Bits Access
Type
Default Description PowerWell ResetSignal
110b: Count 4915 cycles
(150ms)
111b: Count 21299 cycles
(650ms)
OSC1_CFG0[3]:
0b: Gate output of oscillator
with LOCK signal
1b: Give out oscillator output
directly
OSC0_CFG0[2]:
Unused
1 RW/P/L 1'h0 Power down signal for
crystal oscillator
(OSC1_PD)
1b: disable
0b: enable
pwr_rst_n
0 RW/P/L 1'h0 RTC Enable Bypass mode
(OSC1_BYP_XTAL_UP)
1b: enable
0b: disable
24.3.1.6 Peripheral Clock Gate Control
(CCU_PERIPH_CLK_GATE_CTL)
MEM Offset (00000000) 18h
Security_PolicyGroup
IntelRsvd False
Size 32 bits
Default 00CF_7DB5h
Bits Access
Type
Default Description PowerWell ResetSignal
31:2
4
RO 8'h00 RSVD (RSVD)
Reserved
23 RW/P 1'b1 ADC pclk clock gate enable
(CCU_ADC_PCLK_EN_SW)
1b: enable
0b: disable
22 RW/P 1'b1 ADC Clock Enable
(CCU_ADC_CLK_EN)
1b: enable
0b: disable