Datasheet

System Control Subsystem
Intel
®
Quark™ microcontroller D2000
January 2016 Datasheet
Document Number: 333577-002EN 409
24.3.1.5 RTC Oscillator Configuration 0 (OSC1_CFG0)
MEM Offset (00000000) 10h
Security_PolicyGroup
IntelRsvd False
Size 32 bits
Default 0000_0000h
Bits Access
Type
Default Description PowerWell ResetSignal
31:1
8
RO 14'h000
0
RSVD (RSVD)
Reserved
17:1
0
RW/P/L 8'h0 Debug mode test bits
(OSC1_XTAL_32K_SET_RE
G2)
OSC1_CFG0[17:10]
Unused
9:2 RW/P/L 8'h0 Debug mode test bits
(OSC1_XTAL_32K_SET_RE
G1)
OSC1_CFG0[9:7]:
000b: Default bias current to
Gm MOS
010b: Increase bias current
by 50%
011b: Increase bias current
by 75%
110b: Decrease bias current
by 50%
111b: Decrease bias current
by 25%
OSC1_CFG0[6:4]:
000b: Counter TM bits :
Default Count :- 9011
Cycles(275ms)
001b: Count 25395 cycles
(775ms)
010b: Count 13107 cycles
(400ms)
011b: Count 29491 cycles
(900ms)
100b: Count 819 cycles
(25ms)
101b: Count 17203 cycles
(525ms)