Datasheet

System Control Subsystem
Intel
®
Quark™ microcontroller D2000
Datasheet January 2016
402 Document Number: 333577-002EN
24.3 Register Detailed Description
24.3.1.1 Hybrid Oscillator Configuration 0 (OSC0_CFG0)
MEM Offset (00000000) 0h
Security_PolicyGroup
IntelRsvd False
Size 32 bits
Default 0000_0000h
Bits Access
Type
Default Description PowerWell ResetSignal
31:24 RW/P/L 8'h0 Test Mode Inputs
(OSC0_HYB_SET_REG4)
OSC0_CFG0[31:28]:
Unused
OSC0_CFG0[27]:
0b: Gate output of oscillator
with LOCK signal
1b: Give out oscillator output
directly
OSC0_CFG0[26:25]:
00b: Silicon oscillator counter
test mode bits 32M/16M/8M
count value =
44/22/6(default)
01b: Count value=68/34/17
10b: Count value=24/12/3
11b: No output
23:16 RW/P/L 8'h0 Test Mode Inputs
(OSC0_HYB_SET_REG3)
OSC0_CFG0[23]:
0b: Default decrease RDAC
code for retention mode
1b: Disable this option and
feed the same code
OSC0_CFG0[22:21]:
00b: crystal oscillator counter
test bits; Count value: 3327
(default)
01b: Count value: 1279
10b: Count value: 7423
11b: Count value: 5375