Datasheet

Introduction
Intel
®
Quark™ microcontroller D2000
Datasheet January 2016
4 Document Number: 333577-002EN
4.6.3 I
2
C Master/Slave IO AC characteristics ...................................... 49
4.6.4 General IO AC characteristics ................................................... 50
4.6.5 JTAG Interface AC characteristics ............................................. 50
5 Register Access Methods ................................................................................. 51
5.1 Fixed Memory Mapped Register Access ................................................... 51
5.2 Register Field Access Types .................................................................. 51
6 Mapping Address Spaces ................................................................................. 53
6.1 Physical Address Space Mappings .......................................................... 53
6.1.1 SoC Memory Map ................................................................... 53
6.2 SoC Fabric .......................................................................................... 55
7 Clocking ....................................................................................................... 57
7.1 Signal Descriptions .............................................................................. 57
7.2 Features ............................................................................................ 57
7.2.1 System Clock - Hybrid Oscillator ............................................... 58
7.2.2 RTC Oscillator ........................................................................ 58
7.2.3 Root Clock Frequency Scaling ................................................... 59
7.2.4 Frequency Scaling .................................................................. 59
7.2.4.1 Peripheral DFS requirements ..................................... 59
7.2.4.2 Flash DFS requirements ............................................ 60
7.2.5 Dynamic Clock Gating ............................................................. 60
7.2.5.1 UART autonomous clock gating (ACG) ......................... 60
7.2.5.2 SPI autonomous clock gating (ACG) ........................... 60
8 Power Management ........................................................................................ 61
8.1 Component Power States ..................................................................... 62
8.1.1 Voltage Regulator ................................................................... 62
8.1.2 CPU ...................................................................................... 63
8.1.3 ADC ..................................................................................... 64
8.1.4 Comparator ........................................................................... 65
8.1.5 32.768 kHz OSC ..................................................................... 65
8.1.6 32 MHz OSC .......................................................................... 66
8.1.7 SRAM ................................................................................... 66
8.1.8 Peripherals ............................................................................ 67
8.2 System Power States ........................................................................... 68
8.2.1 System Power State Diagram ................................................... 68
8.2.2 System Power State Definition ................................................. 69
8.2.3 Power and Latency Requirements ............................................. 70
8.2.4 Minimum Voltage Limits (Vmin) ................................................ 71
8.3 Power Architecture .............................................................................. 72
8.4 Power Management Unit (PMU) ............................................................. 74
8.4.1 Internal Voltage Regulator ....................................................... 74
8.4.2 External Voltage Regulator ...................................................... 75
9 Power Up and Reset Sequence ......................................................................... 76
9.1 Power Up Sequences ........................................................................... 76
9.1.1 RST_N Triggered Transition to ACTIVE state ............................... 76
9.1.2 Low Power State to Active ....................................................... 77
9.2 Power Down Sequences ....................................................................... 78
9.2.1 Active to Any Low Power State ................................................. 80
9.2.2 Power Sequence Analog Characteristics ..................................... 83
9.2.3 Handling Power Failures .......................................................... 83