Datasheet

Interrupt Routing
Intel
®
Quark™ microcontroller D2000
Datasheet January 2016
396 Document Number: 333577-002EN
Interrupt Vectors 0 to 31 are due to events internal to the Host Processor, interrupts
due to SoC events are routed through the User Defined Interrupts.
The User Defined Interrupts are delivered to the Host Processor via the PIC which
maps particular Interrupt Inputs (IRQs) to configured Interrupt Vectors before
presenting the interrupt to the Processor. The SoC Interrupt table shows the IRQ
number into the PIC rather than the hardwired Interrupt Vector.
23.1.2 SoC Interrupts and Routing
Unused IRQs (63-51) in Table 54 are Reserved. Interrupts have fixed high priority.
Higher the IRQ number, higher is its priority.
Table 56. SoC Interrupt List and Routing Capability
Interrupt
Source
Interrupt
Source
Description Host
Processor
IRQ No.
Host
Processor
Halt for
Debug
I2C MST 0 I2C MST 0 I2C Master 0 Single
Interrupt
36 Y
SPI MST 0 SPI MST 0 SPI Master 0 Single
Interrupt
39 Y
SPI SLV SPI SLV SPI Slave Single
Interrupt
37 Y
UART 0 UART 0 UART 0 Single
Interrupt
40 Y
UART 1 UART 1 UART 1 Single
Interrupt
38 Y
GPIO GPIO GPIO Single Interrupt 47 Y
Timer Timer Timer Single Interrupt 43 Y
RTC RTC RTC Single Interrupt 34 Y
Watchdog Watchdog Watchdog Interrupt 48 Y
DMA
Channel 0
DMA
Channel 0
DMA Channel 0 Single
Interrupt
45 Y
DMA
Channel 1
DMA
Channel 1
DMA Channel 1 Single
Interrupt
44 Y
Comparators
[18:0]
Comparators
[18:0]
19 Comparators
Routed to Single
Interrupt with 19bit
Mask per Destination
46 Y
System System LMT Host AHB Bus
Error
33 Y
DMA
Error[1:0]
DMA
Error[1:0]
2 DMA Channel Error
Interrupts Routed to
Single Interrupt with
8bit Mask per
Destination
32 Y