Datasheet

Analog to Digital Convertor (ADC)
Intel
®
Quark™ microcontroller D2000
Datasheet January 2016
388 Document Number: 333577-002EN
Bits Access
Type
Default Description PowerWell ResetSignal
Reserved
4:0 RW 5'h0 Channel[4N+0]
(Channel_0)
ADC Channel: this bit field
defines the ADC channel to
sample
22.4.1.2 ADC Command Register (ADC_CMD)
MEM Offset (00000000) 20h
Security_PolicyGroup
IntelRsvd False
Size 32 bits
Default 0000_0000h
This register returns 0x0 value when ADC Calibration & Conversion is in IDLE state
waiting for a new command. When a command is written and is not completed yet
(state machine not in IDLE state), then reading back this register returns value
written as part of issuance of command.
Bits Acces
s
Type
Defau
lt
Description PowerW
ell
ResetSign
al
31:2
4
RW 8'h0 SW - Sample Window (SW)
when the ADC command is a
conversion command, this bit field
defines the length of the sample
interval in ADC clocks.
sel is held constant for the sample
window defined here before soc is
asserted. When repeated or
continuous conversions are
commanded,
the next sample interval begins on
the Nth + 2 ADC clock following
start of conversion and ends after
the first clock of the next
conversion
where N is the number of bits of
precision. The sample interval
should be lengthened in case of a
high impedance source (see
Synopsys ADC data book).
This field is encoded thusly:
sampleInterval=SW+2,
sampleRate=adcFreq/(N+sampleInt
erval)
23 RO 1'h0 RSVD (RSVD)
Reserved