Datasheet

Analog to Digital Convertor (ADC)
Intel
®
Quark™ microcontroller D2000
January 2016 Datasheet
Document Number: 333577-002EN 387
Bits Access
Type
Default Description PowerWell ResetSignal
Subsequent conversions will
begin at the start of the
table.
30:29 RO 2'h0 RSVD (RSVD)
Reserved
28:24 RW 5'h0 Channel[4N+3]
(Channel_3)
ADC Channel: this bit field
defines the ADC channel to
sample
23 RW 1'h1 Last[4N+2] (Last_2)
Last Channel when set, this
bit indicates that this is the
last channel in the sequence.
Subsequent conversions will
begin at the start of the
table.
22:21 RO 2'h0 RSVD (RSVD)
Reserved
20:16 RW 5'h0 Channel[4N+2]
(Channel_2)
ADC Channel: this bit field
defines the ADC channel to
sample
15 RW 1'h1 Last[4N+1] (Last_1)
Last Channel when set, this
bit indicates that this is the
last channel in the sequence.
Subsequent conversions will
begin at the start of the
table.
14:13 RO 2'h0 RSVD (RSVD)
Reserved
12:8 RW 5'h0 Channel[4N+1]
(Channel_1)
ADC Channel: this bit field
defines the ADC channel to
sample
7 RW 1'h1 Last[4N+0] (Last_0)
Last Channel when set, this
bit indicates that this is the
last channel in the sequence.
Subsequent conversions will
begin at the start of the
table.
6:5 RO 2'h0 RSVD (RSVD)