Datasheet

Analog to Digital Convertor (ADC)
Intel
®
Quark™ microcontroller D2000
Datasheet January 2016
386 Document Number: 333577-002EN
22.4 Memory Mapped IO Registers
Registers listed are for ADC, starting at base address B0004000h.
Table 54. Summary of ADC Registers0xB0004000
MEM
Address
Default Instance Name Name
0x0 8080_8080h ADC_SEQ[0] ADC Channel Sequence Table
0x4 8080_8080h ADC_SEQ[1] ADC Channel Sequence Table
0x8 8080_8080h ADC_SEQ[2] ADC Channel Sequence Table
0xC 8080_8080h ADC_SEQ[3] ADC Channel Sequence Table
0x10 8080_8080h ADC_SEQ[4] ADC Channel Sequence Table
0x14 8080_8080h ADC_SEQ[5] ADC Channel Sequence Table
0x18 8080_8080h ADC_SEQ[6] ADC Channel Sequence Table
0x1C 8080_8080h ADC_SEQ[7] ADC Channel Sequence Table
0x20 0000_0000h ADC_CMD ADC Command Register
0x24 0000_0000h ADC_INTR_STATUS ADC Interrupt Status Register
0x28 0000_0000h ADC_INTR_ENABLE ADC Interrupt Enable
0x2C 0000_0000h ADC_SAMPLE ADC Sample Register
0x30 0000_0000h ADC_CALIBRATION ADC Calibraton Data Register
0x34 0000_0000h ADC_FIFO_COUNT ADC FIFO Count Register
0x38 0000_0FA0h ADC_OP_MODE ADC Operating Mode Register
22.4.1.1 ADC Channel Sequence Table (ADC_SEQ [0..7])
MEM Offset (00000000) [0]:0h [1]:4h [2]:8h [3]:0Ch
[4]:10h [5]:14h [6]:18h [7]:1Ch
Security_PolicyGroup
IntelRsvd False
Size 32 bits
Default 8080_8080h
Bits Access
Type
Default Description PowerWell ResetSignal
31 RW 1'h1 Last[4N+3] (Last_3)
Last Channel when set, this
bit indicates that this is the
last channel in the sequence.