Datasheet

Analog to Digital Convertor (ADC)
Intel
®
Quark™ microcontroller D2000
Datasheet January 2016
384 Document Number: 333577-002EN
• Current Consumption:
o ~18 uA at 10 kSPS
o ~240 uA at 1 MSPS
o ~1.1 mA at 5 MSPS
o ~15 uA standby
o ~2 uA powerdown
Notes:
1. ADC Hard macro takes in adcclk in the range of 140 kHz to 32 MHz. Minimum
clock frequency is 140 kHz. adcclk is derived from system clock by configuring
CCU_PERIPH_CLK_DIV_CTL0.CCU_ADC_CLK_DIV register in SCSS.
2. ADC Hard macro at its max sampling rate takes selres resolution + 2 cycles.
For 12-bit resolution, it takes 14 cycles to get a sample. To read the sample
by processor/DMA, it takes 3 system clock cycles minimum. Depending on
number of cycles spent by processor for interrupt servicing and to process a
given set of samples, max achievable sampling rate at system level could be
lesser than or equal to max possible sampling rate (12-bit at 2.28 MSps, 10-
bit at 2.6 MSps, 8-bit at 3.2 MSps and 6 bits at 4 MSps).
3. Minimum sampling rate is a function of adclk’s min frequency of 140 kHz =
140 kHz / (selres + 2). Additionally there is a sampling window SW[7:0]
register to delay sampling. For any sampling rate below this limit, software
has to time and then trigger conversion accordingly.
22.3 Use
After powerup/cold reset, ADC is in deep power down state. Depending on current
consumption and entry/exit latencies involved, firmware can put the ADC in different
power states. When ADC is not in use, it is better to put it in low power states to
reduce current consumption.
Power
State
Definition Max
Current
Entry
Latency
Exit
Latency
How Triggered
ON Normal Operation. ADC is enabled for
conversation with optionally enabled
internal LDO. Enadc=H, enldo=H,
dislvl=L. powerup time: 3-5-10 usec
(min-typ-max).
220 uA
@ avdd,
20 uA @
dvdd at
1 MSps
- - Writing to
ADC_OP_MODE
register
STBY Standby Mode. ADC is disabled but ADC
state is kept enabled by enabling
internal LDO and retaining DVDD.
Enadc=L, enldo=H, dislvl=L. Exit
involves 1 conversion cycle.
15 uA @
avdd, 1
uA @
dvdd
- 14 CLK
cycles
Writing to
ADC_OP_MODE
register
PD Power Down mode. ADC is disabled,
calibration state is retained, DVDD is
present, internal LDO is off. Enadc=L,
enldo=L, dislvl=L. A calibrated
conversion cycle can start immediately
after internal LDO Power Up time.
1 uA @
avdd, 1
uA @
dvdd
- 10 usec Writing to
ADC_OP_MODE
register