Datasheet

Real Time Clock (RTC)
Intel
®
Quark™ microcontroller D2000
Datasheet January 2016
378 Document Number: 333577-002EN
20.4.1.6 Interrupt Raw Status Register (RTC_RSTAT)
MEM Offset (B0000400) 14h
Security_PolicyGroup
IntelRsvd False
Size 32 bits
Default 0000_0000h
Bits Access
Type
Default Description PowerWell
31:1 RO 31'h0 Reserved (RSVD1)
Reserved
0 RO 1'h0 RTC RSTAT (RTC_RSTAT)
This register is the raw interrupt status 0 =
interrupt is inactive 1 = interrupt is active
20.4.1.7 End of Interrupt Register (RTC_EOI)
MEM Offset (B0000400) 18h
Security_PolicyGroup
IntelRsvd False
Size 32 bits
Default 0000_0000h
Bits Access
Type
Default Description PowerWell
31:1 RO 31'h0 Reserved (RSVD1)
Reserved
0 RO 1'h0 RTC EOI (RTC_EOI)
By reading this location the match interrupt is
cleared